Intel Cyclone 10 GX User Manual

2.6.3. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core
2.6.3.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core
The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP core implements the
Ethernet protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard. The PHY
IP core consists of a physical coding sublayer (PCS) function and an embedded
physical media attachment (PMA). You can dynamically switch the PHY operating
speed.
Note: Intel FPGAs implement and support the required Media Access Control (MAC) and PHY
(PCS+PMA) IP to interface in a chip-to-chip or chip-to-module channel with external
MGBASE-T and NBASE-T PHY standard devices. You are required to use an external
PHY device to drive any copper media.
Figure 54. Block Diagram of the PHY IP Core
Soft PCS Hard PCS
PMA
Configuration
Registers
Avalon-MM
Interface
TX
XGMII
1G/2.5G/5G/10G Multi-rate Ethernet PHY
Native PHY Hard IP
TX Serial
RX Serial
Hard IP
Soft Logic
Legend
Intel Device with Serial Transceivers
LL Ethernet
10G MAC
User
Application
PLL
for 10 GbE
RX
XGMII
322-MHz
Reference Clock
External
PHY
Transceiver
Reset
Controller
Related Information
• Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26
• Recommended Reset Sequence on page 246
• Low Latency Ethernet 10G MAC Intel FPGA IP User Guide
Describes the Low Latency Ethernet 10G MAC Intel FPGA IP core.
• Low Latency Ethernet 10G MAC Intel Cyclone 10 GX FPGA IP Design Example User
Guide
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English