Intel Cyclone 10 GX User Manual

2.6.3.1.1. Features
Table 100. PHY Features
Feature Description
Multiple operating speeds 10M, 100M, 1G, 2.5G, 5G, and 10G.
MAC-side interface 32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII).
Network-side interface 10.3125 Gbps for 10M/100M/1G/2.5G/5G/10G (USXGMII).
Avalon
®
Memory-Mapped (Avalon-MM)
interface
Provides access to the configuration registers of the PHY.
PCS function USXGMII PCS for 10M/100M/1G/2.5G/5G/10G.
Auto-negotiation USXGMII Auto-negotiation supported in the 10M/100M/1G/2.5G/5G/10G
(USXGMII) configuration.
Sync-E Provides the clock for Sync-E implementation.
2.6.3.1.2. Release Information
Table 101. PHY Release Information
Item Description
Version 18.1
Release Date September 2018
Ordering Codes IP-10GMRPHY
Product ID 00E4
Vendor ID 6AF7
Open Core Plus Supported
2.6.3.1.3. Device Family Support
Table 102. Intel FPGA IP Core Device Support Levels
Device Support Level Definition
Preliminary Intel verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing
timing analysis for the device family. This IP core can be used in production
designs with caution.
Final Intel verifies the IP core with final timing models for this device family. The IP
core meets all functional and timing requirements for the device family. This IP
core is ready to be used in production designs.
Device Family Operating Mode Support Level
Intel Cyclone 10 GX 10M/100M/1G/2.5G/5G/10G Final
2.6.3.1.4. Resource Utilization
The following estimates are obtained by compiling the PHY IP core with the Intel
Quartus Prime software.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English