Intel Cyclone 10 GX User Manual

Parameter Range Description
Enable RX polarity
inversion
On / Off
When you turn on this option, the rx_std_polinv port inverts
the polarity of RX parallel data. When you turn on this
parameter, you also need to enable Enable rx_polinv port.
Enable rx_polinv port On / Off
When you turn on this option, the rx_polinv input is enabled.
You can use this control port to swap the positive and negative
signals of a serial differential link if they were erroneously
swapped during board layout.
Enable rx_std_signaldetect
port
On / Off When you turn on this option, the optional
rx_std_signaldetect output port is enabled. This signal is
required for the PCI Express protocol. If enabled, the signal
threshold detection circuitry senses whether the signal level
present at the RX input buffer is above the signal detect
threshold voltage that you specified. You can specify the signal
detect threshold using a Quartus Prime Assignment Editor or by
modifying the Quartus Settings File (.qsf)
Table 31. PCIe Ports
Parameter Range Description
Enable PCIe dynamic
datarate switch ports
On / Off
When you turn on this option, the pipe_rate, pipe_sw, and
pipe_sw_done ports are enabled. You should connect these ports
to the PLL IP core instance in multi-lane PCIe Gen2 configurations.
The pipe_sw and pipe_sw_done ports are only available for
multi-lane bonded configurations.
Enable PCIe
pipe_hclk_in and
pipe_hclk_out ports
On / Off
When you turn on this option, the pipe_hclk_in, and
pipe_hclk_out ports are enabled. These ports must be
connected to the PLL IP core instance for the PCI Express
configurations.
Enable PCIe electrical
idle control and status
ports
On / Off
When you turn on this option, the pipe_rx_eidleinfersel and
pipe_rx_elecidle ports are enabled. These ports are used for
PCI Express configurations.
Enable PCIe
pipe_rx_polarity port
On / Off
When you turn on this option, the pipe_rx_polarity input
control port is enabled. You can use this option to control channel
signal polarity for PCI Express configurations. When the Standard
PCS is configured for PCIe, the assertion of this signal inverts the
RX bit polarity. For other Transceiver configuration rules the
optional rx_polinv port inverts the polarity of the RX bit stream.
2.4.6. PCS Direct
Table 32. PCS Direct Datapath Parameters
Parameter Range Description
PCS Direct interface width 8, 10, 16, 20, 32, 40, 64 Specifies the data interface width between the PLD and
the transceiver PMA.
2.4.7. Dynamic Reconfiguration Parameters
Dynamic reconfiguration allows you to change the behavior of the transceiver channels
and PLLs without powering down the device. Each transceiver channel and PLL
includes an Avalon-MM slave interface for reconfiguration. This interface provides
direct access to the programmable address space of each channel and PLL. Because
each channel and PLL includes a dedicated Avalon-MM slave interface, you can
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
45

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English