Intel Cyclone 10 GX User Manual

Figure 16. Transceiver Channel Datapath and Clocking for Interlaken
This figure assumes the serial data rate is 12.5 Gbps and the PMA width is 40 bits.
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Parallel Clock (312.5 MHz)
Parallel Clock (312.5 MHz)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
Serial Clock (6.25 GHz)
(6.25 GHz) =
Data rate/2
Input Reference Clock
64 bits
data +
3 bits
control
64 bits
data +
3 bits
control
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
186.57 MHz
to 312.5MHz
186.57 MHz
to 312.5MHz
Enhanced PCS
TX FIFO
Enhanced PCS
RX FIFO
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
FPGA
Fabric
tx_coreclkin
tx_clkout
Div 40
40
40
Related Information
• Interlaken Protocol Definition v1.2
• Interlaken Look-Aside Protocol Definition, v1.1
2.5.1. Metaframe Format and Framing Layer Control Word
The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words.
However, for stability and performance, Intel recommends you set the frame length to
no less than 128 words. In simulation, use a smaller metaframe length to reduce
simulation times. The payload of a metaframe could be pure data payload and a
Burst/Idle control word from the MAC layer.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
71

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English