Intel Cyclone 10 GX User Manual

Table 187. Register Map for CTLE Settings
CTLE Feature Address Bits Values Description
DC Gain 0x11C,
0x11A
[3:0], [7:0] 12’b000000000000
12’b111000000000
12’b111111000000
12’b111111111000
12’b111111111111
Sets the DC gain values. This
register can only be controlled when
in Four stage mode.
CTLE AC Gain Four
Stage
0x167 [5:1] 5’b00000 – 5’b11100 Sets the AC gain value when four
stage mode (High gain mode) is
selected.
VGA SEL 0x160 [3:1] 3’b000 – 3’b100 Sets the VGA Gain value
Related Information
• Steps to Perform Dynamic Reconfiguration on page 328
• Cyclone 10 GX PMA Architecture on page 272
6.12.3. Enabling and Disabling Loopback Modes Using Direct
Reconfiguration Flow
Cyclone 10 GX devices have three loopback modes:
• Serial Loopback
• Reverse Serial Loopback (Pre-CDR)
• Reverse Serial Loopback (Post-CDR)
The loopback mode can be dynamically reconfigured by accessing the register space.
Serial Loopback Mode
In serial loopback mode, a path exists between the serializer of the transmitter and
the CDR of the receiver, so that the data from the CDR is recovered from the serializer
while the data from the receiver serial input pin is ignored. You can enable or disable
this mode.
Figure 214. Serial Loopback Mode
PCS PMA
Serializer
PCS PMA
Deserializer
Transmitter
Receiver
CDR
Serial Loopback
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English