Intel Cyclone 10 GX User Manual

Table 174. Cyclone 10 GX Dynamic Reconfiguration Feature Support
Reconfiguration Features
Channel Reconfiguration PMA analog features
• V
OD
• Pre-emphasis
• Continuous Time Linear Equalizer (CTLE)
TX PLL
• TX local clock dividers
• TX PLL switching
RX CDR
• RX CDR settings
• RX CDR reference clock switching
Reconfiguration of PCS blocks within the datapath
Datapath switching
• Standard, Enhanced, PCS Direct
PLL Reconfiguration PLL settings
• Counters
PLL reference clock switching
Related Information
Unsupported Features on page 371
6.2. Interacting with the Reconfiguration Interface
Each transceiver channel and PLL contains an Avalon Memory-Mapped (Avalon-MM)
reconfiguration interface. The reconfiguration interface provides direct access to the
programmable space of each channel and PLL. Communication with the channel and
PLL reconfiguration interface requires an Avalon-MM master. Because each channel
and PLL has its own dedicated Avalon-MM interface, you can dynamically modify
channels either concurrently or sequentially, depending on how the Avalon-MM master
is connected to the Avalon-MM reconfiguration interface.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English