Intel Cyclone 10 GX User Manual

Figure 210. Writing to the Reconfiguration Interface
reconfig_address
reconfig_write
reconfig_waitrequest
reconfig_read
reconfig_readdata
2
1
reconfig_writedata
reconfig_clk
1. The master asserts the reconfig_address, reconfig_write, and reconfig_writedata signals.
2. The slave (channel or PLL) captures reconfig_writedata, ending the transfer.
119h
0000000c
Note: You must check for the internal configuration bus arbitration before performing
reconfiguration. Refer to the Arbitration section for more details about requesting
access to and returning control of the internal configuration bus from PreSICE.
Related Information
• Arbitration on page 325
• Ports and Parameters on page 346
6.3. Configuration Files
The Cyclone 10 GX Transceiver Native PHY and Transmit PLL IP cores optionally allow
you to save the parameters you specify for the IP instances as configuration files. The
configuration file stores addresses and data values for that specific IP instance.
The configuration files are generated during IP generation. They are located in the <IP
instance name>/reconfig/ subfolder of the IP instance. The configuration data is
available in the following formats:
• SystemVerilog packages: <name>.sv
• C Header files: <name>.h
• Memory Initialization File (MIF): <name>.mif
Select one or more of the configuration file formats on the Dynamic
Reconfiguration tab of the Transceiver Native PHY or Transmit PLL parameter editor
to store the configuration data. All configuration files generated for a particular IP
instance contain the same address and data values. The contents of the configuration
files can be used to reconfigure from one transceiver /PLL configuration to another.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English