6.6. Arbitration
Figure 211. Cyclone 10 GX ATX PLL with Embedded Streamer
User
Reconfiguration
Logic
Streamer
ADME
Configuration
Registers
Avalon-MM
To/From
PreSICE
Interface
Optional Reconfiguration Logic
(Capability, Control and Status)
Cyclone 10 GX ATX PLL
Internal
Configuration
Bus
Cyclone 10 GX ATX PLL IP
Debug Fabric
Host Link
Intel IP
Connectivity to channel reconfiguration registers
and optional soft registers
User Logic
Arbitration
Arbitration
Reconfiguration
Interface
Figure 212. Cyclone 10 GX Native PHY with Embedded Streamer
User
Reconfiguration
Logic
Streamer
ADME
Channel
Configuration
Registers
Avalon-MM
To/From
PreSICE
Interface
Optional Reconfiguration Logic
(Capability, Control and Status,
PRBS Soft Accumulators
Cyclone 10 GX Transceiver
Internal
Configuration
Bus
Cyclone 10 GX Native PHY
Debug Fabric
Host Link
Intel IP
Connectivity to channel reconfiguration registers
and optional soft registers
User Logic
Arbitration
Arbitration
Reconfiguration
Interface
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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Intel
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Cyclone
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10 GX Transceiver PHY User Guide
325