Intel Cyclone 10 GX User Manual

6. Reconfiguration Interface and Dynamic
Reconfiguration
Dynamic reconfiguration is the process of dynamically modifying transceiver channels
and PLLs to meet changing requirements during device operation. Cyclone 10 GX
transceiver channels and PLLs are fully customizable, allowing a system to adapt to its
operating environment. You can customize channels and PLLs by dynamically
triggering reconfiguration during device operation or following power-up. Dynamic
reconfiguration is available for Cyclone 10 GX Transceiver Native PHY, fPLL, ATX PLL,
and CMU PLL IP cores.
Use the reconfiguration interface to dynamically change the transceiver channel or PLL
settings for the following applications:
• Fine tuning signal integrity by adjusting TX and RX analog settings
• Enabling or disabling transceiver channel blocks, such as the PRBS generator and
the checker
• Changing data rates to perform auto negotiation in CPRI, SATA, or SAS
applications
• Changing data rates in Ethernet (1G/10G) applications by switching between
standard and enhanced PCS datapaths
• Changing TX PLL settings for multi-data rate support protocols such as CPRI
• Changing RX CDR settings from one data rate to another
• Switching between multiple TX PLLs for multi-data rate support
The Native PHY and Transmit PLL IP cores provide the following features that allow
dynamic reconfiguration:
• Reconfiguration interface
• Configuration files
• Feature to add PMA analog settings (optional) to the Configuration files (Native
PHY only)
• Multiple reconfiguration profiles (Native PHY and ATX PLL)
• Embedded reconfiguration streamer (Native PHY and ATX PLL)
• Altera Debug Master Endpoint (ADME)
• Optional reconfiguration logic
6.1. Reconfiguring Channel and PLL Blocks
The following table lists some of the available dynamic reconfiguration features in
Cyclone 10 GX devices.
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English