Intel Cyclone 10 GX User Manual

Figure 75. Connection Guidelines for a CPRI PHY Design
PLL IP Core
Data
Generator
Data
Verifier
Cyclone 10 GX Transceiver Native PHY
Reset Controller
rx_cdr_refclk
tx_serialclk0
pll_locked
pll_sel
reset
clk
pll_refclk
tx_ready
rx_ready
tx_parallel_data
tx_clkout
rx_parallel_data
rx_clkout
tx_serial_data
rx_serial_data
rx_is_lockedtodata rx_cal_busy tx_cal_busy tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
pll_cal_busy
8. Simulate your design to verify its functionality.
2.8.5. Native PHY IP Parameter Settings for CPRI
Table 135. General and Datapath Options
The first two sections of the Parameter Editor for the Native PHY IP provide a list of general and datapath
options to customize the transceiver.
Parameter
Value
Message level for rule violations error
warning
Transceiver configuration rules CPRI (Auto)
CPRI (Manual)
PMA configuration rules basic
Transceiver mode TX/RX Duplex
Number of data channels 1-12
Data rate
1228.8 Mbps
2457.6 Mbps
3072 Mbps
4915.2 Mbps
6144 Mbps
Enable datapath and interface reconfiguration Off
Enable simplified data interface On
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English