Intel Cyclone 10 GX User Manual

Figure 74. Signals and Ports of Native PHY IP for CPRI
Reconfiguration
Registers
NIOS
Hard Calibration IP
TX PMA
Cyclone 10 Transceiver Native PHY
Serializer
tx_serial_data
tx_serial_clk0
(from TX PLL)
rx_cal_busy
tx_cal_busy
rx_serial_data
rx_is_lockedtodata
rx_is_lockedtoref
rx_cdr_refclk0
tx_datak
tx_parallel_data
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
tx_datak[1:0]
tx_digital_reset
tx_parallel_data[15:0]
reconfig_clk
reconfig_avmm
reconfig_reset
tx_coreclkin
tx_clkout
RX PMA
TX Standard PCS
RX Standard PCS
Deserializer
Local Clock
Generation
Block
CDR
rx_datak
rx_parallel_data
rx_clkout
rx_coreclkin
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_std_wa_patternalign
unused_rx_parallel_data[118:0]
rx_datak[1:0]
rx_digital_reset
rx_analog_reset
tx_analog_reset
rx_parallel_data[15:0]
rx_clkout
rx_coreclkin
rx_errdetect[1:0]
rx_disperr[1:0]
rx_runningdisp[1:0]
rx_patterndetect[1:0]
rx_syncstatus[1:0]
rx_std_wa_patternalign
10/20
10/20
unused_rx_parallel_data[118:0]
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller.
You can use your own reset controller or use the Native PHY Reset Controller IP.
7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the
information in the following figure to connect the ports.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English