Intel Cyclone 10 GX User Manual

Note: To successfully complete the calibration process, the reference clocks driving the PLLs
(ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA
configuration. Otherwise, recalibration will be necessary.
Related Information
• Calibration on page 373
• Cyclone 10 GX Device Family Pin Connection Guidelines
4.3. How Do I Reset?
You reset a transceiver PHY or PLL by integrating a reset controller in your system
design to initialize the PCS and PMA blocks. You can save time by using the Intel-
provided Transceiver PHY Reset Controller IP core, or you can implement your own
reset controller that follows the recommended reset sequence. You can design your
own reset controller if you require individual control of each signal for reset or need
additional control or status signals as part of the reset functionality.
You can choose from two models for resetting the transceivers, based on your
applications:
• Model 1—Default model (Minimum Assertion Time Requirement)
Choose the Cyclone 10 GX Default Settings preset for the Transceiver PHY
Reset Controller IP.
• Model 2—Acknowledgment model
This model uses an event-driven mechanism. The model is used for applications
with strict timing requirements.
4.3.1. Model 1: Default Model
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English