Intel Cyclone 10 GX User Manual

Bit Offset Address Description
0x100, PreSICE may not set this bit to 0x1, and cal_busy will
remain high. Channel reset is triggered if cal_busy is connected
to the reset controller.
When Read:
• 1'b1: calibration done
• 1'b0: calibration not done
When Write:
• 1'b1: If user doesn't want to trigger calibration (with bit-0 1'b0
or 1'b1)
• 1'b0: To trigger calibration (by also writing 1'b1 to bit-0)
The cal_busy signal is activated two clock cycles after you write
0x0 to this bit.
Note: During calibration when Nios
®
(PreSICE) is controlling the internal configuration bus,
you can not read offset address 0x0. However, you can write 0x0 to offset address
0x0[0] to request bus access.
7.2.2. Transceiver Channel Calibration Registers
Table 207. Transceiver Channel PMA Calibration Registers
Bit PMA Calibration Enable Register Offset Address 0x100
0 Reserved
1 PMA RX calibration enable. Set 1, to enable calibration.
(33)
2 Reserved
3 Reserved
4 Reserved
5 PMA TX calibration enable. Set 1, to enable calibration.
6 Adaptation mode. Set 0, to disable adaptation mode.
7 Reserved
7.2.3. Fractional PLL Calibration Registers
Table 208. Fractional PLL Calibration Registers
Bit fPLL Calibration Enable Register Offset Address 0x100
0 Reserved
1 fPLL calibration enable. Set 1 to enable calibration.
(33)
CDR/CMU PLL calibration is part of PMA RX calibration.
7. Calibration
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English