To disable the PRP verifier, write the original values back to the read-modify-write
addresses listed above.
Related Information
Steps to Perform Dynamic Reconfiguration on page 328
6.17. Timing Closure Recommendations
Intel recommends that you enable the multiple reconfiguration profiles feature in the
Native PHY IP core if any of the modified or target configurations involve changes to
PCS settings. Using multiple reconfiguration profiles is optional if the reconfiguration
involves changes to only PMA settings such as PLL switching, CGB divider switching,
and refclk switching. When you enable multiple reconfiguration profiles, the Quartus
Prime TimeQuest Timing Analyzer includes the necessary PCS timing arcs for all
profiles (initial profile and target profiles) during timing driven compilation. These
timing arcs make the timing more accurate.
When performing a dynamic reconfiguration, you must:
• Include constraints to create the extra clocks for all modified or target
configurations at the PCS-FPGA fabric interface. Clocks for the base configuration
are created by the Quartus Prime software. These clocks enable the Quartus Prime
software to perform static timing analysis for all the transceiver configurations and
their corresponding FPGA fabric core logic blocks.
• Include the necessary false paths between the PCS – FPGA fabric interface and the
core logic.
For example, you can perform dynamic reconfiguration to switch the datapath from
Standard PCS to Enhanced PCS using the multiple reconfiguration profiles feature. In
the following example, the base configuration uses the Standard PCS (data rate =
1.25 Gbps, PCS-PMA width = 10) and drives core logic A in the FPGA fabric. The target
or modified configuration is configured to use the Enhanced PCS (data rate = 10.3125
Gbps, PCS-PMA width = 64) and drives core logic B in the FPGA fabric.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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