Intel Cyclone 10 GX User Manual

3.3.3. xN Clock Lines
The xN clock lines route the transceiver clocks across multiple transceiver banks.
The master CGB drives the x6 clock lines and the x6 clock lines drive the xN clock
lines. There are two xN clock lines: xN Up and xN Down. xN Up clock lines route the
clocks to transceiver banks located above the master CGB and xN Down clock lines
route the clocks to transceiver banks located below the master CGB. The xN clock
lines can be used in both bonded and non-bonded configurations. For bonded
configurations, the low speed parallel clock output of the master CGB is used, and the
local CGB within each channel is bypassed. For non-bonded configurations, the master
CGB provides a high speed serial clock output to each channel.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English