Intel Cyclone 10 GX

Figure 126. xN Clock Network
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
x6
Top
Master
CGB1
Master
CGB0
xN Up xN Down
x6
Bottom
xN Up
xN Down
CMU or CDR
CMU or CDR
Related Information
• Implementing x6/xN Bonding Mode on page 236
• x6/xN Bonding on page 222
• Cyclone 10 GX Data Sheet.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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