Intel Cyclone 10 GX User Manual

Parameter Value
Enable RX data polarity inversion On / Off
Enable tx_enh_bitslip port Off
Enable rx_bitslip port Off
Table 80. Dynamic Reconfiguration Parameters
Parameter Value
Enable dynamic reconfiguration On / Off
Share reconfiguration interface On / Off
Enable Altera Debug Master Endpoint On / Off
Separate reconfig_waitrequest from the status of
AVMM arbitration with PreSICE
On / Off
Enable capability registers On / Off
Set user-defined IP indentifier: 0 to 255
Enable control and status registers On / Off
Enable prbs soft accumulators On / Off
Table 81. Configuration Files Parameters
Parameter Value
Configuration file prefix —
Generate SystemVerilog package file On / Off
Generate C header file On / Off
Generate MIF (Memory Initialization File) On / Off
Include PMA analog settings in configuration files On / Off
Table 82. Configuration Profiles Parameters
Parameter Value
Enable multiple reconfiguration profiles On / Off
Enable embedded reconfiguration streamer On / Off
Generate reduced reconfiguration files On / Off
Number of reconfiguration profiles 1 to 8
Selected reconfiguration profile 1 to 7
2.6. Ethernet
The Ethernet standard comprises many different PHY standards with variations in
signal transmission medium and data rates. The 1G/10GbE and 10GBASE-R PHY IP
Core enables Ethernet connectivity at 1 Gbps and 10 Gbps.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English