Intel Cyclone 10 GX User Manual

Usage Examples for pll_select
•
If a single channel can switch between three TX PLLs, the pll_select signal
indicates which one of the selected three TX PLL's pll_locked signal is used to
communicate the PLL lock status to the TX reset sequence. In this case, to select
the 3-bits wide pll_locked port, the pll_select port is 2-bits wide.
• If three channels are instantiated with three TX PLLs and with a separate TX reset
sequence per channel, the pll_select field is 6-bits wide (2-bits per channel).
In this case, pll_select [1:0] represents channel 0, pll_select[3:2]
represents channel 1, and pll_select[5:4] represents channel 2. For each
channel, a separate pll_locked signal indicates the PLL lock status.
• If three channels are instantiated with three TX PLLs and with a single TX reset
sequence for all three channels, then pll_select field is 2-bits wide. In this
case, the same pll_locked signal indicates the PLL lock status for all three
channels.
•
If one channel is instantiated with one TX PLL, pll_select field is 1-bit wide.
Connect pll_select to logic 0.
• If three channels are instantiated with only one TX PLL and with a separate TX
reset sequence per channel, the pll_select field is 3-bits wide. In this case,
pll_select should be set to 0 since there is only one TX PLL available.
4.4.4. Transceiver PHY Reset Controller Resource Utilization
This section describes the estimated device resource utilization for two configurations
of the transceiver PHY reset controller. The exact resource count varies by Quartus
Prime version number, as well as by optimization options.
Table 161. Reset Controller Resource Utilization
Configuration Combination ALUTs Logic Registers
Single transceiver channel approximately 50 approximately 50
Four transceiver channels, shared TX reset, separate RX resets approximately 100 approximately 150
4.5. Using a User-Coded Reset Controller
You can design your own user-coded reset controller instead of using Transceiver PHY
Reset Controller. Your user-coded reset controller must provide the following
functionality for the recommended reset sequence:
• A clock signal input for your reset logic
• Holds the transceiver channels in reset by asserting the appropriate reset control
signals
•
Checks the PLL status (for example, checks the status of pll_locked and
pll_cal_busy)
Note:
You must ensure a stable reference clock is present at the PLL transmitter before
releasing pll_powerdown.
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English