Intel Cyclone 10 GX User Manual

Signal Name Direction Clock Domain Description
tx_analogreset[<n>-1:
0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Analog reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when reset is asserted.
This signal follows pll_powerdown, which is
deasserted after pll_locked goes high.
tx_ready[<n>-1:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Status signal to indicate when the TX reset sequence is
complete. This signal is deasserted while the TX reset
is active. It is asserted a few clock cycles after the
deassertion of tx_digitalreset. Some protocol
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of TX channels.
rx_digitalreset[<n>
-1:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Digital reset for RX. The width of this signal depends
on the number of channels. This signal is asserted
when any of the following conditions is true:
•
reset is asserted
•
rx_analogreset is asserted
•
rx_cal_busy is asserted
•
rx_is_lockedtodata is deasserted and
rx_manual is deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
rx_digitalreset.
rx_analogreset
[<n>-1:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Analog reset for RX. When asserted, resets the RX CDR
and the RX PMA blocks of the transceiver PHY. This
signal is asserted when any of the following conditions
is true:
•
reset is asserted
•
rx_cal_busy is asserted
The width of this signal depends on the number of
channels.
rx_ready[<n>-1:0]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Status signal to indicate when the RX reset sequence is
complete. This signal is deasserted while the RX reset
is active. It is asserted a few clock cycles after the
deassertion of rx_digitalreset. Some protocol
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of RX channels.
pll_powerdown[<p>-1:0
]
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Asserted to power down a transceiver PLL circuit. When
asserted, the selected TX PLL is reset.
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
Send Feedback
266

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English