Intel Cyclone 10 GX User Manual

6.11. Reconfiguration Flow for Special Cases
Dynamic reconfiguration can be performed on logical operations such as switching
between multiple transmit PLLs or multiple reference clocks. In these cases,
configuration files alone cannot be used. Configuration files are generated during IP
generation and do not contain information on the placement of PLLs or reference
clocks.
To perform dynamic reconfiguration on logical operations, you must use lookup
registers that contain information about logical index to physical index mapping.
Lookup registers are read-only registers. Use these lookup registers to perform a
read-modify-write to the selection MUXes to switch between PLLs or reference clocks.
To perform dynamic reconfiguration using reconfiguration flow for special cases:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the desired lookup register. Refer to the Switching Transmitter PLL and
Switching Reference Clocks sections for information about lookup registers.
3. Perform Logical Encoding (only required for Transmitter PLL switching).
4. Perform read-modify-write to the required feature address with the desired/
encoded value.
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 328
• Switching Transmitter PLL on page 333
• Switching Reference Clocks on page 335
• Resetting Transceiver Channels on page 243
• Calibration on page 373
6.11.1. Switching Transmitter PLL
Dynamically switching data rates increases system flexibility to support multiple
protocols. You can change the transceiver channel data rate by switching from one
transmit PLL to another. To switch between transmit PLLs, you must reconfigure the
local CGB MUX select lines of the channel by performing a channel reconfiguration.
You can clock transceiver channels with up to four different transmitter PLLs. You can
use the reconfiguration interface on the Native PHY IP core to specify which PLL drives
the transceiver channel. The PLL switching method is the same, regardless of the
number of transmitter PLLs involved.
Before initiating the PLL switch procedure, ensure that your Transceiver Native PHY
instance defines more than one transmitter PLL input. Specify the Number of TX PLL
clock inputs per channel parameter on the TX PMA tab during Transceiver Native
PHY parameterization.
The following table shows the addresses and bits for transmitter PLL switching. The
number of exposed tx_serial_clk bits varies according to the number of
transmitter PLLs you specify. Use the Native PHY reconfiguration interface for this
operation.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English