Intel Cyclone 10 GX User Manual

File Name Description
<your_ip_name> .bsf A Block Symbol File (.bsf) for your Transceiver Native PHY
instance.
<project_dir>/<your_ip_name>/ The directory that stores the HDL files that define the
Transceiver Native PHY IP.
<project_dir>/sim The simulation directory.
<project_dir>/sim/aldec Simulation files for Riviera-PRO simulation tools.
<project_dir>/sim/cadence Simulation files for Cadence simulation tools.
<project_dir>/sim/mentor Simulation files for Mentor simulation tools.
<project_dir>/sim/synopsys Simulation files for Synopsys simulation tools.
<project_dir>/synth The directory that stores files used for synthesis.
The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the
following simulators:
• ModelSim SE
• Synopsys VCS MX
• Cadence NCSim
If you select VHDL for your transceiver PHY, only the wrapper generated by the
Quartus Prime software is in VHDL. All the underlying files are written in Verilog or
SystemVerilog. To enable simulation using a VHDL-only ModelSim license, the
underlying Verilog and SystemVerilog files for the Transceiver Native PHY IP are
encrypted so that they can be used with the top-level VHDL wrapper without using a
mixed-language simulator.
For more information about simulating with ModelSim, refer to the Mentor Graphics
ModelSim Support chapter in volume 3 of the Quartus Prime Handbook.
The Transceiver Native PHY IP cores do not support the NativeLink feature in the
Quartus Prime software.
Related Information
Mentor Graphics ModelSim Support
2.4.12. Unused Transceiver Channels
To prevent performance degradation of unused transceiver channels over time, the
following assignments for RX pins must be added to an Cyclone 10 GX device QSF. You
can either use a global assignment or per-pin assignment. For the per-pin assignment,
true or complement RX pin can be specified.
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
or
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to
[pin_name (BB6, for example)]
Example of <pin_name> is AF26 (Do not use PIN_AF26)
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
69

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English