Intel Cyclone 10 GX User Manual

Figure 15. Directory Structure for Generated Files
<Project Directory>
<your_ip_or_system_name>.qsys - Top-level IP variation file
<your_ip_or_system_name>.sopcinfo
<your_ip_name> - IP core variation files
<your_ip_name>.cmp - VHDL component declaration file
<your_ip_name>_bb - Verilog HDL black-box EDA synthesis file
<your_ip_name>_inst - IP instantiation template file
<your_ip_name>.ppf - XML I/O pin information file
<your_ip_name>.qip - Lists IP synthesis files
<your_ip_name>.sip - Lists files for simulation
<your_ip_name>.v or .vhd - Greybox timing netlist
synth - IP synthesis files
<your_ip_name>.v or .vhd - Top-level IP synthesis file
sim - IP simulation files
<your_ip_name>.v or .vhd - Top-level simulation file
aldec- Simulator setup scripts
<IP subcore> - IP subcore files
<HDL files>
sim
cadence - Simulator setup scripts
mentor - Simulator setup scripts
synopsys - Simulator setup scripts
<HDL files>
synth
The following table describes the directories and the most important files for the
parameterized Transceiver Native PHY IP core and the simulation environment. These
files are in clear text.
Table 68. Transceiver Native PHY Files and Directories
File Name Description
<project_dir> The top-level project directory.
<your_ip_name> .v or .vhd The top-level design file.
<your_ip_name> .qip A list of all files necessary for Quartus Prime compilation.
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English