Intel Cyclone 10 GX User Manual

Parameters Value Description
Enable rx_pma_clkslip
port
On/Off
Enables the optional rx_pma_clkslip control input port. A rising
edge on this signal causes the RX serializer to slip the serial data
by one clock cycle, or 2 unit intervals (UI).
Enable
rx_is_lockedtodata
port
On/Off
Enables the optional rx_is_lockedtodata status output port.
This signal indicates that the RX CDR is currently in lock to data
mode or is attempting to lock to the incoming data stream. This is
an asynchronous output signal.
Enable
rx_is_lockedtoref port
On/Off
Enables the optional rx_is_lockedtoref status output port.
This signal indicates that the RX CDR is currently locked to the
CDR reference clock. This is an asynchronous output signal.
Enable
rx_set_lockedtodata
port and
rx_set_lockedtoref
ports
On/Off
Enables the optional rx_set_lockedtodata and
rx_set_lockedtoref control input ports. You can use these
control ports to manually control the lock mode of the RX CDR.
These are asynchronous input signals.
Enable rx_seriallpbken
port
On/Off
Enables the optional rx_seriallpbken control input port. The
assertion of this signal enables the TX to RX serial loopback path
within the transceiver. This is an asynchronous input signal.
Enable PRBS (Pseudo
Random Bit Sequence)
verifier control and
status port
On/Off
Enables the optional rx_prbs_err, rx_prbs_clr, and
rx_prbs_done control ports. These ports control and collect
status from the internal PRBS verifier.
2.4.4. Enhanced PCS Parameters
This section defines parameters available in the Native PHY IP core GUI to customize
the individual blocks in the Enhanced PCS.
The following tables describe the available parameters. Based on the selection of the
Transceiver Configuration Rule , if the specified settings violate the protocol
standard, the Native PHY IP core Parameter Editor prints error or warning
messages.
Note: For detailed descriptions about the optional ports that you can enable or disable, refer
to the Enhanced PCS Ports section.
Table 12. Enhanced PCS Parameters
Parameter Range Description
Enhanced PCS / PMA
interface width
32, 40, 64 Specifies the interface width between the Enhanced PCS and the
PMA.
FPGA fabric /Enhanced
PCS interface width
32, 40, 64, 66, 67 Specifies the interface width between the Enhanced PCS and the
FPGA fabric.
The 66-bit FPGA fabric to PCS interface width uses 64-bits from the
TX and RX parallel data. The block synchronizer determines the
block boundary of the 66-bit word, with lower 2 bits from the
control bus.
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English