Intel Cyclone 10 GX User Manual

Parameter Value Description
Use this feature when you want to dynamically re-configure CDR
reference clock source.
Selected CDR reference
clock
0 to <number of
CDR reference
clocks> -1
Specifies the initial CDR reference clock. This parameter
determines the available CDR references used.
The default value is 0.
Selected CDR reference
clock frequency
< data rate
dependent >
Specifies the CDR reference clock frequency. This value depends
on the data rate specified.
PPM detector threshold 100
300
500
1000
Specifies the PPM threshold for the CDR. If the PPM between the
incoming serial data and the CDR reference clock, exceeds this
threshold value, the CDR loses lock.
The default value is 1000.
Table 10. Equalization
Parameters Value Description
CTLE adaptation mode Manual Specifies the Continuous Time Linear Equalization (CTLE)
operation mode.
For manual mode, set the CTLE options through the Assignment
Editor, or modify the Quartus Settings File (.qsf), or write to the
reconfiguration registers using the Avalon Memory-Mapped
(Avalon-MM) interface.
Refer to the Continuous Time Linear Equalization (CTLE) section
for more details about CTLE architecture. Refer to the How to
Enable CTLE section for more details on supported adaptation
modes.
Table 11. RX PMA Optional Ports
Parameters Value Description
Enable
rx_analog_reset_ack
port
On/Off
Enables the optional rx_analog_reset_ack output. This port
should not be used for register mode data transfers.
Enable rx_pma_clkout
port
On/Off
Enables the optional rx_pma_clkout output clock. This port is
the recovered parallel clock from the RX clock data recovery
(CDR).
(12)
Enable
rx_pma_div_clkout
port
On/Off
Enables the optional rx_pma_div_clkout output clock. The
deserializer generates this clock. Use this to drive core logic, to
drive the RX PCS-to-FPGA fabric interface, or both.
If you select a rx_pma_div_clkout division factor of 1 or 2, this
clock output is derived from the PMA parallel clock. If you select a
rx_pma_div_clkout division factor of 33, 40, or 66, this clock is
derived from the PMA serial clock. This clock is commonly used
when the interface to the RX FIFO runs at a different rate than the
PMA parallel clock frequency, such as 66:40 applications.
rx_pma_div_clkout
division factor
Disabled, 1, 2, 33, 40,
66
Selects the division factor for the rx_pma_div_clkout output
clock when enabled.
(13)
Enable
rx_pma_iqtxrx_clkout
port
On/Off
Enables the optional rx_pma_iqtxrx_clkout output clock. This
clock can be used to cascade the RX PMA output clock to the input
of a PLL.
continued...
(12)
This clock should not be used to clock the FPGA - transceiver interface. This clock may be used
as a reference clock to an external clock cleaner.
(13)
The default value is Disabled.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
33

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English