Intel Cyclone 10 GX User Manual

1.2.4. Clock Generation Block (CGB)
In Intel Cyclone 10 GX devices, there are two types of clock generation blocks (CGBs):
• Master CGB
• Local CGB
Transceiver banks with six transceiver channels have two master CGBs. Master CGB1
is located at the top of the transceiver bank and master CGB0 is located at the bottom
of the transceiver bank. The master CGB divides and distributes bonded clocks to a
bonded channel group. It also distributes non-bonded clocks to non-bonded channels
across the x6/xN clock network.
Each transceiver channel has a local CGB. The local CGB is used for dividing and
distributing non-bonded clocks to its own PCS and PMA blocks.
Related Information
Clock Generation Block on page 216
1.3. Calibration
Intel Cyclone 10 GX FPGAs contain a dedicated calibration engine to compensate for
process variations. The calibration engine calibrates the analog portion of the
transceiver to allow both the transmitter and receiver to operate at optimum
performance.
The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the
CLKUSR clock must be free running and stable at the start of FPGA configuration to
successfully complete the calibration process and for optimal transceiver performance.
Note:
For more information about CLKUSR electrical characteristics, refer to Intel Cyclone 10
GX Device Datasheet. The CLKUSR can also be used as an FPGA configuration clock.
For information about configuration requirements for the CLKUSR pin, refer to the
Configuration, Design Security, and Remote System Upgrades in Intel Cyclone 10 GX
Devices chapter in the Intel Cyclone 10 GX Core Fabric and General-Purpose I/O
Handbook. For more information about calibration, refer to the Calibration chapter. For
more information about CLKUSR pin requirements, refer to the Intel Cyclone 10 GX
Device Family Pin Connection Guidelines.
Related Information
• Calibration on page 373
• Intel Cyclone 10 GX Device Datasheet
• Configuration, Design Security, and Remote System Upgrades in Intel Cyclone 10
GX Devices
• Intel Cyclone 10 GX Device Family Pin Connection Guidelines
1. Intel
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Cyclone
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10 GX Transceiver PHY Overview
UG-20070 | 2018.09.24
Intel
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Cyclone
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English