Intel Cyclone 10 GX User Manual

Parameter Value Description
High-Speed Compensation Enable / Disable Enables the power-distribution network (PDN) induced inter-
symbol interference (ISI) compensation in the TX driver.
When enabled, it reduces the PDN induced ISI jitter, but
increases the power consumption.
On-Chip termination r_r1, r_r2 Selects the on-chip TX differential termination.
RX Analog PMA settings
Override Intel-recommended
Default settings
On / Off Enables the option to override the Intel-recommended
settings for one or more RX analog parameters. For details
about QSF assignments for the analog settings, refer to the
Analog Parameter Settings chapter.
CTLE (Continuous Time Linear
Equalizer) mode
non_s1_mode Selects RX high gain mode (non_s1_mode) for the
Continuous Time Linear Equalizer (CTLE).
DC gain control of high gain
mode CTLE
no_dc_gain to
stg4_gain7
Selects the DC gain of the Continuous Time Linear Equalizer
(CTLE) in high gain mode
AC Gain Control of High Gain
Mode CTLE
radp_ctle_acgain_4s_0
to
radp_ctle_acgain_4s_2
8
Selects the AC gain of the Continuous Time Linear Equalizer
(CTLE) in high gain mode when CTLE is in manual mode
Variable Gain Amplifier (VGA)
Voltage Swing Select
radp_vga_sel_0 to
radp_vga_sel_4
Selects the Variable Gain Amplifier (VGA) output voltage
swing when the CTLE block is in manual mode.
Related Information
• Analog Parameter Settings on page 388
• Embedded Debug Features on page 353
• Arbitration on page 325
• Changing PMA Analog Parameters on page 338
• Calibration on page 373
6.14. Dynamic Reconfiguration Interface Merging Across Multiple
IP Blocks
Dynamic reconfiguration interfaces may need to be shared between multiple IP blocks
to maximize transceiver channel utilization. The Native PHY provides the ability to
create channels that are either simplex or duplex instances. However, each physical
transceiver channel in Cyclone 10 GX devices is fully duplex.
You can share the reconfiguration interfaces across different IP blocks by manually
making a QSF assignment. There are two cases where a dynamic reconfiguration
interface might need to be shared between multiple IP blocks:
• Independent instances of simplex receivers and transmitters in the same physical
location
• Separate CMU PLL and TX channel in the same physical location
The following example shows one Native PHY IP instance of a TX-only channel and
another instance of an RX-only channel.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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Intel
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Cyclone
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10 GX Transceiver PHY User Guide
351

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English