Intel Cyclone 10 GX User Manual

Figure 218. Independent Instances of Simplex TX/RX in the Same Physical Location
Reconfiguration
Interface 0
TX Channel
RX Channel
User Logic
Native PHY IP Core
Native PHY IP Core
Logical
User Logic
Native PHY IP Core
Physical
TX Channel
RX Channel
Reconfiguration Interface 0 merged into
Reconfiguration Interface1
Merging QSF: from Reconfiguration Interface 0
to Reconfiguration Interface 1
Reconfiguration
Interface 1
Reconfiguration
Interface 1
The following example shows one Native PHY IP instance of a TX-only channel and an
instance of a CMU PLL.
Figure 219. Separate CMU PLL and TX Channel in the Same Physical Location
CMU
TX Channel
User Logic
Transceiver PLL IP Core
Native PHY IP Core
Logical
User Logic
Native PHY IP Core
Physical
CMU
TX Channel
Reconfiguration Interface 1 merged into
Reconfiguration Interface 0
Merging QSF: from Reconfiguration Interface 1
to Reconfiguration Interface 0
Reconfiguration
Interface 0
Reconfiguration
Interface 0
Reconfiguration
Interface 1
Rules for Merging Reconfiguration Interfaces Across Multiple IP Cores
To merge reconfiguration interfaces across multiple IP blocks, you must follow these
rules:
1. The control signals for the reconfiguration interfaces of the IP blocks must be
driven by the same source. The reconfig_clk, reconfig_reset,
reconfig_write, reconfig_read, reconfig_address, and
reconfig_writedata ports of the two interfaces to be merged must be driven
from the same source.
2. You must make a QSF assignment to manually specify which two reconfiguration
interfaces are to be merged.
a. Use the XCVR_RECONFIG_GROUP assignment.
b. Set the To field of the assignment to either the reconfiguration interfaces of
the instances to be merged or to the pin names. The reconfiguration interface
has the string twentynm_hssi_avmm_if_inst.
c. Assign the two instances to be merged to the same reconfiguration group.
You cannot merge multiple reconfiguration interfaces when ADME, optional
reconfiguration logic, or embedded reconfiguration streamer are enabled in the Native
PHY IP core.
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6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English