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General| Brand | Intel |
|---|---|
| Model | Cyclone 10 GX |
| Category | Transceiver |
| Language | English |
Describes the dedicated calibration engine to compensate for process variations.
Guides on selecting and instantiating the appropriate PHY IP core for protocol implementation.
Describes the two methods for resetting transceivers in Cyclone 10 GX devices.
Explains how to make analog parameter settings using Assignment Editor or Quartus Prime Settings File.
Explains the use of the Intel-provided Cyclone 10 GX Transceiver Native PHY IP core.
Explains how to change transceiver channels and PLLs without powering down the device.
Guides on implementing Interlaken protocol PHY layer.
Guides on implementing GbE and GbE with IEEE 1588v2 protocols.
Guides on implementing 10GBASE-R and 10GBASE-R with IEEE 1588v2.
Guides on implementing PCI Express solution using Cyclone 10 GX transceivers.
Describes dynamic switching between Gen1 and Gen2 data rates.
Guides on connecting TX PLLs for PIPE Gen1 and Gen2 modes.
Guides on implementing PCI Express solution using Native PHY IP.
Guides on placing channels for PIPE configurations, considering hardware restrictions.
Details the deterministic latency state machine in the word aligner for CPRI.
Explains word aligner behavior in manual mode for CPRI.
Guides on implementing CPRI protocol.
Guides on configuring Enhanced PCS for 10G or 10G-like protocols using Basic.
Guides on implementing Basic (Enhanced PCS) transceiver configuration rules.
Guides on enabling low latency in Basic Enhanced PCS.
Guides on implementing Basic and Basic with Rate Match configurations.
Guides on implementing PCS Direct transceiver configuration rule.
Describes the transceiver phase locked loops (PLLs), internal clocking architecture, and clocking options.
Lists the five possible input reference clock sources for Cyclone 10 GX transceiver PLLs.
Describes clock signals from FPGA fabric to transceiver and vice versa.
Explains the two types of bonding modes available for Cyclone 10 GX devices.
Details the x6/xN bonding mode process.
Explains PLL feedback compensation bonding mode.
Guides on using PLLs and clock networks for transceiver design.
Guides on implementing single channel x1 non-bonded configuration.
Guides on implementing multi-channel x1 non-bonded configuration.
Guides on implementing multi-channel xN non-bonded configuration.
Guides on implementing x6/xN bonded configuration.
Guides on implementing PLL feedback compensation bonding mode.
Guides on implementing PLL cascading.
Details the conditions that require a transceiver reset.
Guides on how to reset transceiver PHY or PLL blocks.
Describes the default reset model with minimum assertion time requirement.
Details the receiver reset sequence during device operation in Auto Mode.
Describes the acknowledgment model using an event-driven mechanism.
Provides the recommended reset sequence for the acknowledgment model.
Details the transmitter reset sequence during device operation with acknowledgment.
Details the receiver reset sequence during device operation.
Guides on dynamic reconfiguration of the transmitter channel using acknowledgment model.
Guides on dynamic reconfiguration of the receiver channel using acknowledgment model.
Guides on using the Transceiver PHY Reset Controller IP core.
Describes the PMA as the analog front end for Cyclone 10 GX transceivers.
Explains how pre-emphasis maximizes the eye at the far-end receiver.
Details how CTLE boosts attenuated signals and supports DC and AC gain.
Guides on how to enable CTLE settings.
Explains how channel PLL can be configured as a receiver clock data recovery (CDR).
Explains CDR operation in LTD mode to recover clock from incoming serial data.
Details the functions provided by the Enhanced PCS for protocols operating at 10 Gbps or higher.
Explains the TX FIFO interface between transmitter channel PCS and FPGA fabric.
Guides on using PRBS pattern generator for simulating traffic.
Explains the Enhanced PCS RX FIFO's function and modes.
Explains the Register Mode bypassing FIFO for stringent latency requirements.
Describes Interlaken mode where RX FIFO operates as deskew FIFO.
Explains the TX FIFO interface and its modes.
Details the low latency mode for TX FIFO.
Explains the register mode for TX FIFO.
Details the fast register mode for TX FIFO.
Explains the word aligner's function and modes.
Details the Word Aligner Bit Slip Mode.
Explains the Word Aligner Manual Mode.
Details the Word Aligner Synchronous State Machine Mode.
Explains the Word Aligner Deterministic Latency Mode.
Guides on using the PRBS checker.
Lists available dynamic reconfiguration features for channels and PLLs.
Explains how to interact with the reconfiguration interface.
Guides on reading values from the reconfiguration interface.
Guides on writing values to the reconfiguration interface.
Guides on enabling multiple configurations or profiles for dynamic reconfiguration.
Explains enabling the embedded reconfiguration streamer for automation.
Provides recommendations for dynamic reconfiguration.
Outlines steps for performing dynamic reconfiguration.
Describes the direct reconfiguration flow for changing specific parameters.
Guides on performing dynamic reconfiguration using IP guided flow.
Details reconfiguration flow for special cases like PLL switching.
Guides on dynamically switching data rates by switching transmit PLLs.
Guides on dynamically switching the input clock source for PLLs.
Explains how to change PMA analog settings using reconfiguration interface.
Guides on changing VOD and Pre-emphasis using direct reconfiguration flow.
Guides on changing CTLE settings in manual mode using direct reconfiguration flow.
Guides on enabling and disabling loopback modes using direct reconfiguration flow.
Explains the ADME for accessing transceiver and PLL registers.
Explains calibration using PreSICE with Avalon-MM interface.
Describes the automatic calibration process at device power-up.
Details when user recalibration is required.
Lists conditions requiring user recalibration.
Outlines the user recalibration sequence.
Provides examples for recalibrating ATX PLL, fPLL, and Native PHY IP.
Guides on recalibrating the ATX PLL after making changes.
Guides on recalibrating the fPLL.
Details PMA recalibration including TX and RX calibration.
Guides on making assignments using the Assignment Editor.
Details analog equalization settings for the receiver.
Details CTLE settings for receiver equalization.
Controls VGA output voltage swing when adaptation mode is manual.
Details pre-emphasis settings for the transmitter buffer.
Controls transmitter programmable output differential voltage swing.
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