Intel Cyclone 10 GX User Manual

5.3.2.1.2. Word Aligner Manual Mode
In manual alignment mode, the word aligner operation is controlled by
rx_std_wa_patternalign. The word aligner operation is edge-sensitive or level-
sensitive to rx_std_wa_patternalign, depending upon the PCS-PMA interface
width selected.
Table 171.
Word Aligner rx_std_wa_patternalign Behavior
PCS-PMA Interface Width
rx_std_wa_patternalign Behavior
8 Rising edge sensitive
10 Level sensitive
16 Rising edge sensitive
20 Rising edge sensitive
If rx_std_wa_patternalign is asserted, the word aligner looks for the
programmed word alignment pattern in the received data stream. It updates the word
boundary if it finds the word alignment pattern in a new word boundary. If
rx_std_wa_patternalign is deasserted, the word aligner maintains the current
word boundary even when it sees the word alignment pattern in a new word
boundary.
The rx_syncstatus and rx_patterndetect signals, with the same latency as the
datapath, are forwarded to the FPGA fabric to indicate the word aligner status.
After receiving the first word alignment pattern after rx_std_wa_patternalign is
asserted, both rx_syncstatus and rx_patterndetect are driven high for one
parallel clock cycle. Any word alignment pattern received thereafter in the same word
boundary causes only rx_patterndetect to go high for one clock cycle. Any word
alignment pattern received thereafter in a different word boundary causes the word
aligner to re-align to the new word boundary only if rx_std_wa_patternalign is
asserted. The word aligner asserts rx_syncstatus for one parallel clock cycle
whenever it re-aligns to the new word boundary.
5.3.2.1.3. Word Aligner Synchronous State Machine Mode
In synchronous state machine mode, when the programmed number of valid
synchronization code groups or ordered sets is received, rx_syncstatus is driven
high to indicate that synchronization is acquired. The rx_syncstatus signal is
constantly driven high until the programmed number of erroneous code groups is
received without receiving intermediate good groups, after which rx_syncstatus is
driven low.
The word aligner indicates loss of synchronization (rx_syncstatus remains low)
until the programmed number of valid synchronization code groups are received
again.
5.3.2.1.4. Word Aligner Deterministic Latency Mode
In deterministic latency mode, the state machine removes the bit level latency
uncertainty. The deserializer of the PMA creates the bit level latency uncertainty as it
comes out of reset.
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English