Intel Cyclone 10 GX User Manual

The PCS performs pattern detection on the incoming data from the PMA. The PCS
aligns the data, after it indicates to the PMA the number of serial bits to clock slip the
boundary.
If the incoming data has to be realigned, rx_std_wa_patternalign must be
reasserted to initiate another pattern alignment. Asserting
rx_std_wa_patternalign can cause the word align to lose synchronization if
already achieved. This may cause rx_syncstatus to go low.
Table 172. PCS-PMA Interface Widths and Protocol Implementations
PCS-PMA Interface Width Protocol Implementations
8 Basic
10 • Basic
• Basic rate match
• CPRI
• PCIe Gen1 and Gen2
• GigE
16 Basic
20 • CPRI
• Basic
• Basic rate match
5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes
Table 173. Word Aligner Pattern Length for Various Word Aligner Modes
PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Supported
Word Aligner
Pattern
Lengths
rx_std_wa_patte
rnalign behavior
rx_syncstatus
behavior
rx_patterndetect
behavior
8 Bit slip 8
rx_std_wa_patt
ernalign has no
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
N/A N/A
Manual 8, 16 Word alignment is
controlled by
rx_std_wa_patt
ernalign and is
edge-sensitive to
this signal.
Asserted high for
one parallel clock
cycle when the
word aligner aligns
to a new boundary.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
10 Bit slip 7
rx_std_wa_patt
ernalign has no
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
N/A N/A
continued...
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English