Home
Intel
Transceiver
Cyclone 10 GX
Intel Cyclone 10 GX User Manual
4
of 1
of 1 rating
402 pages
Give review
Manual
Specs
To Next Page
To Next Page
To Previous Page
To Previous Page
Loading...
PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Supported
Word Aligner
Pattern
Lengths
rx_std_wa_patte
rnalign
behavior
rx_syncstatus
behavior
rx_patterndetect
behavior
FPGA fabric-
asserted BITSLIP
signal toggles.
Manual
7, 10
Word alignment is
controlled by
rx_std_wa_patt
ernalign
and is
level-sensitive to
this signal.
Asserted high for
one parallel clock
cycle when the
word aligner aligns
to a new boundary
.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary
.
Deterministic latency
(CPRI mode only)
10
W
ord alignment is
controlled by
rx_std_wa_patt
ernalign
(edge-
sensitive to this
signal) and the
state machine
works in
conjunction with
PMA to achieve
deterministic
latency on the RX
path for CPRI and
OBSAI applications.
—
—
Synchronous State
Machine
7, 10
rx_std_wa_patt
ernalig
n has no
effect on word
alignment.
Stays high as long
as the
synchronization
conditions are
satisfied.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary
.
16
Bit slip
16
rx_std_wa_patt
ernalign
has no
effect on word
alignment. The
double width word
aligner updates the
word boundary
,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
N/A
N/A
Manual
8, 16, 32
Word alignment is
controlled by
rising-edge of
rx_std_wa_patt
ernalign
.
Stays high after
the word aligner
aligns to the word
alignment pattern.
Goes low on
receiving a rising
edge on
rx_std_wa_patt
ernalign
until a
new word
alignment pattern
is received.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary
.
20
Bit slip
7
rx_std_wa_patt
ernalign
has no
effect on word
alignment. The
N/A
N/A
continued...
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX T
ransceiver PHY User Guide
Send Feedback
308
307
309
Table of Contents
Default Chapter
2
Table of Contents
2
1 Intel ® Cyclone ® 10 GX Transceiver PHY Overview
7
Device Transceiver Layout
8
Intel Cyclone 10 GX Device Transceiver Layout
8
Intel Cyclone 10 GX Device Package Details
10
Transceiver PHY Architecture Overview
10
Transceiver Bank Architecture
10
PHY Layer Transceiver Components
11
Transceiver Phase-Locked Loops
13
Clock Generation Block (CGB)
14
Calibration
14
Intel Cyclone 10 GX Transceiver PHY Overview Revision History
15
2 Implementing Protocols in Intel Cyclone 10 GX Transceivers
16
Transceiver Design IP Blocks
16
Transceiver Design Flow
17
Select and Instantiate the PHY IP Core
17
Configure the PHY IP Core
19
Generate the PHY IP Core
19
Select the PLL IP Core
19
Configure the PLL IP Core
20
Generate the PLL IP Core
21
Reset Controller
21
Create Reconfiguration Logic
21
Connect the PHY IP to the PLL IP Core and Reset Controller
22
Connect Datapath
22
Make Analog Parameter Settings
22
Compile the Design
22
Verify Design Functionality
22
Cyclone 10 GX Transceiver Protocols and PHY IP Support
24
Using the Cyclone 10 GX Transceiver Native PHY IP Core
26
Presets
28
General and Datapath Parameters
28
PMA Parameters
31
Enhanced PCS Parameters
34
Standard PCS Parameters
41
PCS Direct
45
Dynamic Reconfiguration Parameters
45
PMA Ports
50
Enhanced PCS Ports
53
Standard PCS Ports
62
IP Core File Locations
67
Unused Transceiver Channels
69
Interlaken
70
Metaframe Format and Framing Layer Control Word
71
Interlaken Configuration Clocking and Bonding
73
How to Implement Interlaken in Cyclone 10 GX Transceivers
79
Native PHY IP Parameter Settings for Interlaken
82
Ethernet
86
Gigabit Ethernet (Gbe) and Gbe with IEEE 1588V2
87
10GBASE-R and 10GBASE-R with IEEE 1588V2 Variants
98
2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP Core
108
XAUI PHY IP Core
121
Acronyms
121
PCI Express (PIPE)
122
Transceiver Channel Datapath for PIPE
123
Supported PIPE Features
123
How to Connect TX Plls for PIPE Gen1 and Gen2 Modes
128
How to Implement PCI Express (PIPE) in Cyclone 10 GX Transceivers
131
Native PHY IP Parameter Settings for PIPE
131
Fpll IP Parameter Core Settings for PIPE
135
ATX PLL IP Parameter Core Settings for PIPE
137
Native PHY IP Ports for PIPE
139
Fpll Ports for PIPE
143
ATX PLL Ports for PIPE
145
How to Place Channels for PIPE Configurations
146
Cpri
149
Transceiver Channel Datapath and Clocking for CPRI
149
Supported Features for CPRI
151
Word Aligner in Manual Mode for CPRI
152
How to Implement CPRI in Cyclone 10 GX Transceivers
153
Native PHY IP Parameter Settings for CPRI
155
Other Protocols
158
Using the "Basic (Enhanced PCS)" Configuration
158
Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS
166
How to Implement PCS Direct Transceiver Configuration Rule
185
Simulating the Transceiver Native PHY IP Core
186
Nativelink Simulation Flow
187
Scripting IP Simulation
192
Custom Simulation Flow
193
Implementing Protocols in Intel Cyclone 10 GX Transceivers Revision History
196
3 Plls and Clock Networks
198
Plls
200
Transmit Plls Spacing Guidelines When Using ATX Plls and Fplls
200
Atx Pll
201
Fpll
203
Cmu Pll
206
Input Reference Clock Sources
208
Dedicated Reference Clock Pins
209
Receiver Input Pins
209
PLL Cascading as an Input Reference Clock Source
210
Reference Clock Network
210
Global Clock or Core Clock as an Input Reference Clock
210
Transmitter Clock Network
210
X1 Clock Lines
211
X6 Clock Lines
212
Xn Clock Lines
214
Clock Generation Block
216
FPGA Fabric-Transceiver Interface Clocking
217
Transmitter Data Path Interface Clocking
219
Receiver Data Path Interface Clocking
220
Unused/Idle Clock Line Requirements
221
Channel Bonding
222
PMA Bonding
222
PMA and PCS Bonding
224
Selecting Channel Bonding Schemes
225
Skew Calculations
226
PLL Feedback and Cascading Clock Network
226
Using Plls and Clock Networks
231
Non-Bonded Configurations
231
Bonded Configurations
235
Implementing PLL Cascading
240
Timing Closure Recommendations
241
Plls and Clock Networks Revision History
241
4 Resetting Transceiver Channels
243
When Is Reset Required
243
Transceiver PHY Implementation
244
How Do I Reset
245
Model 1: Default Model
245
Model 2: Acknowledgment Model
254
Transceiver Blocks Affected by Reset and Powerdown Signals
258
Using the Transceiver PHY Reset Controller
259
Parameterizing the Transceiver PHY Reset Controller IP
261
Transceiver PHY Reset Controller Parameters
261
Transceiver PHY Reset Controller Interfaces
264
Transceiver PHY Reset Controller Resource Utilization
267
Using a User-Coded Reset Controller
267
User-Coded Reset Controller Signals
268
Combining Status or PLL Lock Signals
269
Timing Constraints for Bonded PCS and PMA Channels
269
Resetting Transceiver Channels Revision History
271
5 Cyclone 10 GX Transceiver PHY Architecture
272
Cyclone 10 GX PMA Architecture
272
Transmitter
272
Receiver
275
Loopback
282
Cyclone 10 GX Enhanced PCS Architecture
283
Transmitter Datapath
284
Receiver Datapath
291
Cyclone 10 GX Standard PCS Architecture
299
Transmitter Datapath
300
Receiver Datapath
305
Intel Cyclone 10 GX Transceiver PHY Architecture Revision History
314
6 Reconfiguration Interface and Dynamic Reconfiguration
315
Reconfiguring Channel and PLL Blocks
315
Interacting with the Reconfiguration Interface
316
Reading from the Reconfiguration Interface
318
Writing to the Reconfiguration Interface
318
Configuration Files
319
Multiple Reconfiguration Profiles
321
Embedded Reconfiguration Streamer
322
Arbitration
325
Recommendations for Dynamic Reconfiguration
327
Steps to Perform Dynamic Reconfiguration
328
Direct Reconfiguration Flow
330
Native PHY IP or PLL IP Core Guided Reconfiguration Flow
331
Reconfiguration Flow for Special Cases
333
Switching Transmitter PLL
333
Switching Reference Clocks
335
Changing PMA Analog Parameters
338
Changing VOD, Pre-Emphasis Using Direct Reconfiguration Flow
341
Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow
342
Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow
343
Ports and Parameters
346
Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks
351
Embedded Debug Features
353
Altera Debug Master Endpoint
354
Optional Reconfiguration Logic
354
Using Data Pattern Generators and Checkers
359
Using PRBS Data Pattern Generator and Checker
359
Using Pseudo Random Pattern Mode
368
Timing Closure Recommendations
369
Unsupported Features
371
Cyclone 10 GX Transceiver Register Map
372
Reconfiguration Interface and Dynamic Reconfiguration Revision History
372
7 Calibration
373
Reconfiguration Interface and Arbitration with Presice Calibration Engine
373
Calibration Registers
375
Avalon-MM Interface Arbitration Registers
375
Transceiver Channel Calibration Registers
376
Fractional PLL Calibration Registers
376
ATX PLL Calibration Registers
377
Capability Registers
377
Rate Switch Flag Register
379
Power-Up Calibration
380
User Recalibration
383
Conditions that Require User Recalibration
383
User Recalibration Sequence
384
Calibration Example
385
ATX PLL Recalibration
385
Fractional PLL Recalibration
385
CDR/CMU PLL Recalibration
386
PMA Recalibration
386
Calibration Revision History
387
8 Analog Parameter Settings
388
Making Analog Parameter Settings Using the Assignment Editor
388
Updating Quartus Settings File with the Known Assignment
388
Analog Parameter Settings List
389
Receiver General Analog Settings
390
Xcvr_C10_Rx_Term_Sel
390
Receiver Analog Equalization Settings
390
CTLE Settings
391
VGA Settings
393
Transmitter General Analog Settings
393
Xcvr_C10_Tx_Term_Sel
394
Xcvr_C10_Tx_Compensation_En
394
Xcvr_C10_Tx_Slew_Rate_Ctrl
395
Transmitter Pre-Emphasis Analog Settings
395
Xcvr_C10_Tx_Pre_Emp_Sign_Pre_Tap_1T
396
Xcvr_C10_Tx_Pre_Emp_Sign_Pre_Tap_2T
396
Xcvr_C10_Tx_Pre_Emp_Sign_1St_Post_Tap
397
Xcvr_C10_Tx_Pre_Emp_Sign_2Nd_Post_Tap
397
Xcvr_C10_Tx_Pre_Emp_Switching_Ctrl_Pre_Tap_1T
398
Xcvr_C10_Tx_Pre_Emp_Switching_Ctrl_Pre_Tap_2T
398
Xcvr_C10_Tx_Pre_Emp_Switching_Ctrl_1St_Post_Tap
399
Xcvr_C10_Tx_Pre_Emp_Switching_Ctrl_2Nd_Post_Tap
399
Transmitter VOD Settings
400
Xcvr_C10_Tx_Vod_Output_Swing_Ctrl
400
Dedicated Reference Clock Settings
401
Xcvr_C10_Refclk_Term_Tristate
401
Xcvr_C10_Tx_Xtx_Path_Analog_Mode
401
Unused Transceiver Channels Settings
402
Analog Parameter Settings Revision History
402
4
Based on 1 rating
Ask a question
Give review
Questions and Answers:
Need help?
Do you have a question about the Intel Cyclone 10 GX and is the answer not in the manual?
Ask a question
Intel Cyclone 10 GX Specifications
General
Brand
Intel
Model
Cyclone 10 GX
Category
Transceiver
Language
English
Related product manuals
Intel Arria 10
607 pages
Intel Cyclone 10 GX FPGA
65 pages
Intel MAX 10 JTAG
14 pages
Intel Stratix 10 FPGA
4 pages
To Next PageTo Next PageTo Previous PageTo Previous Page
Loading...
Need help?
General
