Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX
Transceivers
2.1. Transceiver Design IP Blocks
Note: Intel Cyclone 10 GX only supported with Intel Quartus Prime Pro Edition 17.1 and
future versions.
Figure 7. Cyclone 10 GX Transceiver Design Fundamental Building Blocks
Transceiver
PLL IP Core
Master/Local
Clock
Generation
Block
Avalon-MM Master
Reset Ports
Analog and Digital
Reset Bus
Reconfiguration
Registers
Avalon-MM
Interface
Non-Bonded and
Bonded Clocks
Transceiver PHY IP Core
(1)
Note:
Transceiver PHY
Reset Controller
(2)
Legend:
Intel generated IP block
User created IP block
MAC IP Core /
Data Generator /
Data Analyzer
Parallel Data Bus
Avalon master allows access to Avalon-MM
reconfiguration registers via the Avalon
Memory Mapped interface. It enables PCS,
PMA , and PLL reconfiguration. To access
the reconfiguration registers, implement an
Avalon master in the FPGA fabric. This faciliates
reconfiguration by performing reads and writes
through the Avalon-MM interface.
Transceiver PLL IP core provides a clock source
to clock networks that drive the transceiver
channels. In Cyclone 10 devices, PLL IP Core
is separate from the transceiver PHY IP core.
Reset controller is used for resetting the
transceiver channels.
This block can be either a MAC IP core, or
a frame generator / analyzer or a
data generator / analyzer.
Transceiver PHY IP core controls the PCS and
PMA configurations and transceiver
channels functions for all communication
protocols.
(1) The Transceiver PHY IP core can be one of the supported PHY IP Cores ( For example: Native PHY IP Core).
(2) You can either design your own reset controller or use the Transceiver PHY Reset Controller.
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English