Intel Cyclone 10 GX User Manual

3.1. PLLs
Table 155. Transmit PLLs in Cyclone 10 GX Devices
PLL Type Characteristics
Advanced Transmit (ATX) PLL • Best jitter performance
• LC tank based voltage controlled oscillator (VCO)
• Used for both bonded and non-bonded channel
configurations
Fractional PLL (fPLL) • Ring oscillator based VCO
• Supports fractional synthesis mode
• Used for both bonded and non-bonded channel
configurations
Clock Multiplier Unit (CMU) PLL or Channel PLL
(27)
• Ring oscillator based VCO
• Used as an additional clock source for non-bonded
applications
Related Information
Refer to Using PLL and Clock Networks section for guidelines and usage on page 231
3.1.1. Transmit PLLs Spacing Guidelines when using ATX PLLs and fPLLs
ATX PLL-to-ATX PLL Spacing Guidelines
ATX PLLs' VCO frequency offset must be 100 MHz apart. If this requirement cannot be
met, use fPLL as transmit PLL to avoid more than one ATX PLL usage. For applications
that requires multi-data rate support, use TX PLL switching or TX local clock dividers
to achieve the desire data rate reconfiguration.
Note: You are not allowed to recalibrate an ATX PLL if there are TX channels driven by
another ATX PLL in transmitting mode.
ATX PLL-to-fPLL Spacing Guidelines
If you are using both ATX PLL and fPLL, and you meet the below two conditions in
your applications:
• When ATX PLL VCO frequency and fPLL VCO frequency is within 50 MHz.
• ATX PLL is used to drive 6G or 12G SDI protocol.
The ATX PLL and fPLL must be separated at least by one ATX PLL in between.
If you are using both ATX PLL and fPLL, and you meet the following two conditions in
your applications:
• fPLL user re-calibration process is triggered.
• ATX PLL is used to drive 6G or 12G SDI protocol.
then the ATX PLL and fPLL must be separated at least by one ATX PLL in between
(regardless of the ATX PLL and fPLL VCO frequency offset).
(27)
The CMU PLL or Channel PLL of channel 1 and channel 4 can be used as a transmit PLL or as a
clock data recovery (CDR) block. The channel PLL of all other channels (0, 2, 3, and 5) can
only be used as a CDR.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
Send Feedback
200

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English