Intel Cyclone 10 GX User Manual

Related Information
PHY Interface For the PCI Express, SATA, and USB 3.1 Architectures
2.7.1. Transceiver Channel Datapath for PIPE
Figure 57. Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations
PIPE Interface
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
PRBS
Verifier
PCI Express Hard IP
2.7.2. Supported PIPE Features
PIPE Gen1 and Gen2 configurations support different features.
Table 118. Supported Features for PIPE Configurations
Protocol Feature Gen1
(2.5 Gbps)
Gen2
(5 Gbps)
x1, x2, x4 link configurations Yes Yes
PCIe-compliant synchronization state machine Yes Yes
Total 600 ppm clock rate compensation between transmitter reference clock
and receiver reference clock
Yes Yes
Transmitter driver electrical idle Yes Yes
Receiver detection Yes Yes
8B/10B encoding/decoding disparity control Yes Yes
Power state management Yes Yes
Receiver PIPE status encoding pipe_rxstatus[2:0]
Yes Yes
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate No Yes
Dynamic transmitter margining for differential output voltage control No Yes
Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB No Yes
PCS PMA interface width (bits) 10 10
Receiver Electrical Idle Inference (EII) Your implementation in
the FPGA fabric
Your
implementation
in the FPGA
fabric
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English