Intel Cyclone 10 GX User Manual

Related Information
Intel PHY Interface for the PCI Express (PIPE) Architecture
2.7.2.1. Gen1/Gen2 Features
In a PIPE configuration, each channel has a PIPE interface block that transfers data,
control, and status signals between the PHY-MAC layer and the transceiver channel
PCS and PMA blocks. The PIPE configuration is based on the PIPE 2.0 specification. If
you use a PIPE configuration, you must implement the PHY-MAC layer in the FPGA
fabric.
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
In a PIPE configuration, Native PHY IP Core provides an input signal pipe_rate
[1:0] that is functionally equivalent to the RATE signal specified in the PCIe
specification. A change in value from 2'b00 to 2'b01 on this input signal pipe_rate
[1:0] initiates a data rate switch from Gen1 to Gen2. A change in value from 2'b01
to 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1.
2.7.2.1.2. Transmitter Electrical Idle Generation
The PIPE interface block in Cyclone 10 GX devices puts the transmitter buffer in an
electrical idle state when the electrical idle input signal is asserted. During electrical
idle, the transmitter buffer differential and common mode output voltage levels are
compliant with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data
rates.
The PCIe specification requires the transmitter driver to be in electrical idle in certain
power states.
Note: For more information about input signal levels required in different power states, refer
to Power State Management section.
Related Information
Power State Management on page 124
2.7.2.1.3. Power State Management
Table 119. Power States Defined in the PCIe Specification
To minimize power consumption, the physical layer device must support the following power states.
Power States
Description
P0 Normal operating state during which packet data is transferred on the PCIe link.
P0s, P1, and P2 The PHY-MAC layer directs the physical layer to transition into these low-power states.
The PIPE interface in Cyclone 10 GX transceivers provides a pipe_powerdown[1:0]
input port for each transceiver channel configured in a PIPE configuration.
The PCIe specification requires the physical layer device to implement power-saving
measures when the P0 power state transitions to the low power states. Cyclone 10 GX
transceivers do not implement these power-saving measures except for putting the
transmitter buffer in electrical idle mode in the lower power states.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
Send Feedback
124

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English