Intel Cyclone 10 GX User Manual

2.2.6. Generate the PLL IP Core
After configuring the PLL IP core, complete the following steps to generate the PLL IP
core.
1. Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2.
In Synthesis options, under Create HDL design for synthesis select Verilog
or VHDL.
3. Select appropriate Simulation options depending on the choice of the hardware
description language you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected
output directory.
5. Click Generate.
The Quartus
®
Prime software generates a <pll ip core instance name> folder, <pll ip
core instance name>_sim folder, <pll ip core instance name>.qip file, <pll ip core
instance name>.qsys, and <pll ip core instance name>.v file or <pll ip core instance
name>.vhd file. The <pll ip core instance name>.v file is the top level design file for
the PLL IP core and is placed in the <pll ip core instance name>/ synth folder. The
other folders contain lower level design files used for simulation and compilation.
Related Information
IP Core File Locations on page 67
For more information about IP core file structure
2.2.7. Reset Controller
There are two methods to reset the transceivers in Cyclone 10 GX devices:
• Use the Transceiver PHY Reset Controller.
• Create your own reset controller that follows the recommended reset sequence.
Related Information
Resetting Transceiver Channels on page 243
2.2.8. Create Reconfiguration Logic
Dynamic reconfiguration is the ability to dynamically modify the transceiver channels
and PLL settings during device operation. To support dynamic reconfiguration, your
design must include an Avalon master that can access the dynamic reconfiguration
registers using the Avalon-MM interface.
The Avalon-MM master enables PLL and channel reconfiguration. You can dynamically
adjust the PMA parameters, such as differential output voltage swing (Vod), and pre-
emphasis settings. This adjustment can be done by writing to the Avalon-MM
reconfiguration registers through the user generated Avalon-MM master.
For detailed information on dynamic reconfiguration, refer to Reconfiguration Interface
and Dynamic Reconfiguration chapter.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
21

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English