Intel Cyclone 10 GX User Manual

2.7.10. ATX PLL Ports for PIPE
Table 129. ATX PLL Ports for PIPE
This section contains the recommended settings for this protocol. Refer to Using the Cyclone 10 GX Transceiver
Native PHY IP Core for the full range of parameter settings.
Port Direction Clock Domain Description
Pll_powerdown
Input Asynchronous Resets the PLL when asserted high. Needs to be connected to
the Transceiver PHY Reset Controller pll_powerdown output.
Pll_reflck0
Input N/A Reference clock input port 0. There are five reference clock
input ports. The number of reference clock ports available
depends on the Number of PLL reference clocks parameter.
tx_serial_clk
Output N/A High speed serial clock output port for GX channels. Represents
the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to the
tx_serial_clk input of the native PHY IP.
For Gen1x2, x4 use the tx_bonding_clocks[5:0] output
port to connect to the Native PHY.
For Gen2x2, x4 use the tx_bonding_clocks[5:0] output
port to connect to the Native PHY.
pll_locked
Output Asynchronous Active high status signal which indicates if PLL is locked.
pll_pcie_clk
Output N/A This is the hclk required for PIPE interface.
For Gen1x1,x2,x4 use this port to drive the pipe_hclk_in on
the PIPE interface.
For Gen2x1,x2,x4 use this port to drive the pipe_hclk_in on
the PIPE interface.
Pll_cal_busy
Output Asynchronous Status signal which is asserted high when PLL calibration is in
progress. If this port is not enabled in the Transceiver PHY
Reset Controller, then perform logical OR with this signal and
the tx_cal_busy output signal from Native PHY to input the
tx_cal_busy on the reset controller IP.
Mcgb_rst
Input Asynchronous Master CGB reset control.
tx_bonding_clocks[5:0]
Output N/A Optional 6-bit bus which carries the low speed parallel clock
outputs from the Master CGB. Used for channel bonding, and
represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2,x4 connect the output from this port to the
tx_bonding_clocks[5:0] input on Native PHY.
For Gen2x1, this port is disabled
For Gen2x2,x4 connect the output from this port to
tx_bonding_clocks[5:0] input on Native PHY.
pcie_sw[1:0]
Input Asynchronous 2-bit rate switch control input used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen 2x2,x4 connect the pipe_sw[1:0] output from Native
PHY to this port.
pcie_sw_done[1:0]
Output Asynchronous 2-bit rate switch status output used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen2x2, x4 connect the pcie_sw_done[1:0] output from
ATX PLL to pipe_sw_done input of Native PHY .
Related Information
Using the Cyclone 10 GX Transceiver Native PHY IP Core on page 26
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English