Intel Cyclone 10 GX User Manual

Related Information
Transmit PLLs Spacing Guidelines when using ATX PLLs and fPLLs on page 200
7.5.3. CDR/CMU PLL Recalibration
CDR/CMU PLL user recalibration is integrated into the PMA RX user recalibration.
Enabling 0x100[1] PMA RX calibration recalibrates the CDR/CMU PLL.
7.5.4. PMA Recalibration
PMA calibration includes:
• PMA TX calibration
• PMA RX calibration
The PMA RX calibration includes CDR/CMU PLL calibration, offset cancellation
calibration, and V
CM
calibration. The TX PMA calibration includes TX termination, Vod,
and DCD calibration.
Follow these steps to recalibrate the PMA:
1. Request access to the internal configuration bus by writing 0x2 to offset address
0x0[7:0].
2.
Wait for reconfig_waitrequest to be deasserted (logic low), or wait until
capability register of PreSICE Avalon-MM interface control 0x281[2]=0x0.
3. Configure the PMA calibration enable register 0x100.
• Read-Modify-Write 0x1 to 0x100[1] to start PMA RX calibration.
• Read-Modify-Write 0x1 to 0x100[5] to start PMA TX calibration.
• Read-Modify-Write 0x0 to 0x100[6] to disable adaptation mode.
4. If there is a data rate change in the CDR, set the rate switch flag register
0x166[7] for PMA RX calibration.
• Read-Modify-Write 0x1 to offset address 0x166[7] if no rate switch.
• Read-Modify-Write 0x0 to offset address 0x166[7] if switched rate with
different CDR bandwidth setting.
Note: Refer to Rate Switch Flag Registerfor more information.
5. Do Read-Modify-Write the proper value to capability register 0x281[5:4] for PMA
calibration to enable/disable tx_cal_busy or rx_cal_busy output.
•
To enable rx_cal_busy, Read-Modify-Write 0x1 to 0x281[5].
•
To disable rx_cal_busy, Read-Modify-Write 0x0 to 0x281[5].
•
To enable tx_cal_busy, Read-Modify-Write 0x1 to 0x281[4].
•
To disable tx_cal_busy, Read-Modify-Write 0x0 to 0x281[4].
Note: Refer to PMA Capability Registers for Calibration Status for more
information.
6. Release the internal configuration bus to PreSICE to perform recalibration by
writing 0x1 to offset address 0x0[7:0].
7.
Periodically check the *cal_busy output signals or read the capability registers
0x281[1:0] to check *cal_busy status until calibration is complete.
7. Calibration
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English