Intel Cyclone 10 GX User Manual

•
set_false_path -from [get_clocks {rx_clkout_enh}] -to
[get_registers <Core Logic A>]
Based on how the clocks are connected in the design, you may have to include
additional constraints to set false paths from the registers in the core logic to the
clocks.
•
set_false_path -from [get_clocks {tx_clkout}] -to
[get_registers <Core Logic B>]
Based on how the clocks are connected in the design, you may have to include
additional constraints to set false paths from the registers in the core logic to the
clocks.
•
set_false_path -from [get_clocks {rx_clkout}] -to
[get_registers <Core Logic B>]
Based on how the clocks are connected in the design, you may have to include
additional constraints to set false paths from the registers in the core logic to the
clocks.
Note: If any of the profile or configuration switch involves switching from FIFO to
the register mode, then the false paths should be set between the PCS-PMA
interface register and the core logic because the common clock point is
within the PCS-PMA interface.
For example, if the base configuration of the above case is configured for the TX and
RX FIFOs in the Register Mode, the following constraint needs to be created:
•
set_false_path -from [get_registers {native:native_inst|
native_altera_xcvr_native_c10_150_lzjn6xi:xcvr_native_c10_0|
twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_nati
ve_inst|
twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|
twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|
gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_p
ld_pcs_interface~pma_tx_pma_clk_reg.reg}] -to [get_registers
<Core Logic B>]
•
set_false_path -from [get_registers {native:native_inst|
native_altera_xcvr_native_c10_150_lzjn6xi:xcvr_native_c10_0|
twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_nati
ve_inst|
twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|
twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|
gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_p
ld_pcs_interface~pma_rx_pma_clk_reg.reg}] -to [get_registers
<Core Logic B>]
6.18. Unsupported Features
The following features are not supported by either the Transceiver Native PHY IP core
or the PLL IP reconfiguration interface:
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-20070 | 2018.09.24
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Intel
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Cyclone
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10 GX Transceiver PHY User Guide
371

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English