Intel Cyclone 10 GX User Manual

Figure 131. Receiver Standard PCS and PMA Clocking
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
rx_serial_data
FPGA
Fabric
/2, /4
Parallel Clock
Serial Clock
Parallel and Serial Clock Parallel and Serial Clock
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
rx_clkout
PRBS
Verifier
All configurations that use the standard PCS channel must have a 0 ppm phase
difference between the receiver datapath interface clock and the read side clock of the
RX phase compensation FIFO.
Figure 132. Receiver Enhanced PCS and PMA Clocking
Receiver PMA
Receiver Enhanced PCS
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
Enhanced PCS
RX FIFO
Interlaken
CRC32 Checker
FPGA
Fabric
Parallel Clock
Serial Clock
Parallel and Serial Clock
The receiver PCS forwards the following clocks to the FPGA fabric:
•
rx_clkout — for each receiver channel when the rate matcher is not used.
•
tx_clkout — for each receiver channel when the rate matcher is used.
You can clock the receiver datapath interface using one of the following methods:
• Quartus Prime selected receiver datapath interface clock
• User-selected receiver datapath interface clock
Related Information
Unused or Idle Clock Line Requirements on page 221
For more information about unused or idle transceiver clock lines in design.
3.8. Unused/Idle Clock Line Requirements
Unused or idle transceiver clock lines can degrade if the devices are powered up to
normal operating conditions and the devices are not configured. This issue also affects
designs that will configure transceiver channels to use the idle clock lines at a later
date by using dynamic reconfiguration or a new device programming file. Clock lines
affected are unused idle receiver (RX) serial clock lines. Active RX serial clock lines
and non-transceiver circuits are not impacted by this issue.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
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Intel
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Cyclone
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10 GX Transceiver PHY User Guide
221

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English