Intel Cyclone 10 GX User Manual

Figure 118. Cyclone 10 GX PLLs and Clock Networks
Local CGB
CDR
CH2
Local CGB
CDR/CMU
CH1
Local CGB
CDR
CH0
fPLL
ATX
PLL
Master
CGB
Local CGB
CDR
CH5
Local CGB
CDR/CMU
CH4
Local CGB
CDR
CH3
fPLL
ATX
PLL
Master
CGB
Local CGB
CDR
CH2
Local CGB
CDR/CMU
CH1
Local CGB
CDR
CH0
fPLL
ATX
PLL
Master
CGB
x1 Clock Lines x6 Clock Lines xN Clock Lines
Transceiver
Bank
Transceiver
Bank
fPLL
ATX
PLL
Master
CGB
Local CGB
CDR
CH3
Related Information
• Channel Bonding on page 222
• Device Transceiver Layout on page 8
• Using PLLs and Clock Networks on page 231
Information on how to use PLL IP to implement bonded and non-bonded
transceiver designs.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
199

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English