Intel Cyclone 10 GX User Manual

PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Supported
Word Aligner
Pattern
Lengths
rx_std_wa_patte
rnalign behavior
rx_syncstatus
behavior
rx_patterndetect
behavior
double width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
Manual 7, 10, 20, 40 Word alignment is
controlled by rising
edge of
rx_std_wa_patt
ernalign.
Stays high after
the word aligner
aligns to the word
alignment pattern.
Goes low on
receiving a rising
edge on
rx_std_wa_patt
ernalign until a
new word
alignment pattern
is received.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
Deterministic latency
(CPRI mode only)
10 Word alignment is
controlled by
rx_std_wa_patt
ernalign (edge-
sensitive to this
signal) and the
deterministic
latency state
machine which
controls the PMA to
achieve
deterministic
latency on the RX
path for CPRI and
OBSAI applications.
— —
Synchronous State
Machine
7, 10, 20 FPGA fabric-driven
rx_std_wa_patt
ernalign signal
has no effect on
word alignment.
Stays high as long
as the
synchronization
conditions are
satisfied.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
5.3.2.1.6. Word Aligner RX Bit Reversal Feature
The RX bit reversal feature reverses the order of the data received from the PMA. It is
performed at the output of the Word Aligner and is available even when the Word
Aligner is disabled. If the data received from the PMA is a 10-bit data width, the bit
reversal feature switches bit [0] with bit [9], bit [1] with bit [8], and so on. For
example, if the 10-bit data is 1000010011, the bit reversal feature, when enabled,
changes the data to 1100100001.
5.3.2.1.7. Word Aligner RX Byte Reversal Feature
The RX byte reversal feature is available only when the PCS-PMA interface width is 16
bits or 20 bits. This feature reverses the order of the data received from the PMA. RX
byte reversal reverses the LSByte of the received data with its MSByte and vice versa.
If the data received is 20-bits, bits[0..9] are swapped with bits[10..20] so that the
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English