Intel Cyclone 10 GX User Manual

channel width two or four times (FPGA fabric-to-PCS interface width) and dividing the
clock (tx_clkout) rate by 2 or 4. The byte serializer can be disabled, or operate in
Serialize x2 or Serialize x4 modes.
Figure 197. Byte Serializer Block Diagram
Byte
Serializer
dataout
(to the 8B/10 Encoder
or the TX Bit Slip)
datain (from the TX FIFO)
/2,
/4
tx_clkout
Related Information
• Resetting Transceiver Channels on page 243
• Implementing Protocols in Intel Cyclone 10 GX Transceivers on page 16
5.3.1.2.1. Bonded Byte Serializer
The bonded byte serializer is available in Cyclone 10 GX devices, and is used in
applications such as PIPE, CPRI, and custom applications where multiple channels are
grouped together. The bonded byte serializer is implemented by bonding all the
control signals to prevent skew induction between channels during byte serialization.
In this configuration, one of the channels acts as master and the remaining channels
act as slaves.
5.3.1.2.2. Byte Serializer Disabled Mode
In disabled mode, the byte serializer is bypassed. The data from the TX FIFO is
directly transmitted to the 8B/10B encoder, TX Bitslip, or Serializer, depending on
whether or not the 8B/10B encoder and TX Bitslip are enabled. Disabled mode is used
in low speed applications such as GigE, where the FPGA fabric and the TX standard
PCS can operate at the same clock rate.
5.3.1.2.3. Byte Serializer Serialize x2 Mode
The serialize x2 mode is used in high-speed applications such as the PCIe Gen1 or
Gen2 protocol implementation, where the FPGA fabric cannot operate as fast as the TX
PCS.
In serialize x2 mode, the byte serializer serializes 16-bit, 20-bit (when 8B/10B
encoder is not enabled), 32-bit, and 40-bit (when 8B/10B encoder is not enabled)
input data into 8-bit, 10-bit, 16-bit, and 20-bit data, respectively. As the parallel data
width from the TX FIFO is halved, the clock rate is doubled.
After byte serialization, the byte serializer forwards the least significant word first
followed by the most significant word. For example, if the FPGA fabric-to-PCS
Interface width is 32, the byte serializer forwards tx_parallel_data[15:0] first,
followed by tx_parallel_data[31:16].
Related Information
PCI Express (PIPE) on page 122
For more information about using the Serialize x2 mode in the PCIe protocol.
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
Send Feedback
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
301

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English