Intel Cyclone 10 GX User Manual

5.2.2.10. Enhanced PCS RX FIFO
The Enhanced PCS RX FIFO is designed to compensate for the phase and/or clock
difference between the receiver channel PCS and the FPGA fabric. It can operate as a
phase-compensation, clock-compensation, elastic buffer, or a deskew FIFO in
Interlaken mode. The RX FIFO has a width of 74 bits and a depth of 32 words for all
protocols.
The RX FIFO supports the following modes:
• Phase Compensation mode
• Register mode
• Interlaken mode (deskew FIFO)
• 10GBASE-R mode (clock compensation FIFO)
• Basic mode (elastic buffer FIFO)
5.2.2.10.1. Phase Compensation Mode
The RX FIFO compensates for the phase difference between the read clock and write
clocks. rx_clkout (RX parallel low-speed clock) clocks the write side of the RX FIFO.
rx_coreclkin (FPGA fabric clock) or rx_clkout clocks the read side of the RX
FIFO.
When phase compensation is used in double-width mode, the FPGA data width is
doubled to allow the FPGA fabric clock to run at half rate, similar to the TX FIFO phase
compensation in double-width mode.
Depth of RX FIFO is constant in this mode, therefore RX FIFO flag status can be
ignored. You can tie tx_enh_data_valid with one.
5.2.2.10.2. Register Mode
The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency
uncertainty for applications with stringent latency requirements. This is accomplished
by tying the read clock of the FIFO with its write clock.
In Register mode, rx_parallel_data (data), rx_control indicates whether
rx_parallel_data is a data or control word, and rx_enh_data_valid (data valid)
are registered at the FIFO output. The RX FIFO in register mode has one register
stage or one parallel clock latency.
Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with minimum of
32 words under the following conditions:
• When the Enhanced PCS RX FIFO is set to register mode.
• When using the recovered clock to drive the core logics.
• When there is no soft FIFO being generated along with the IP Catalog.
5.2.2.10.3. Interlaken Mode
In Interlaken mode, the RX FIFO operates as an Interlaken deskew FIFO. To
implement the deskew process, implement an FSM that controls the FIFO operation
based on available FPGA input and output flags.
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English