Intel Cyclone 10 GX User Manual

Figure 190. PRP Verifier
Error
Counter
Test Pattern
Detect
Pseudo Random
Verifier
error_count
Descrambler
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for
configuration details.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 315
5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker
The 10GBASE-R BER checker block is designed in accordance with the 10GBASE-R
protocol specification as described in IEEE 802.3-2008 clause-49. After block lock
synchronization is achieved, the BER checker starts to count the number of invalid
synchronization headers within a 125-μs period. If more than 16 invalid
synchronization headers are observed in a 125-μs period, the BER checker provides
the status signal rx_enh_highber to the FPGA fabric, indicating a high bit error rate
condition.
When the optional control input rx_enh_highber_clr_cnt is asserted, the internal
counter for the number of times the BER state machine has entered the
"BER_BAD_SH" state is cleared.
When the optional control input rx_enh_clr_errblk_count is asserted, the
internal counter for the number of times the RX state machine has entered the "RX_E"
state for the 10GBASE-R protocol is cleared.
Note: The 10GBASE-R BER checker is available to implement the 10GBASE-R protocol.
5.2.2.9. Interlaken CRC-32 Checker
The Interlaken CRC-32 checker verifies that the data transmitted has not been
corrupted between the transmit PCS and the receive PCS. The CRC-32 checker
calculates the 32-bit CRC for the received data and compares it against the CRC value
that is transmitted within the diagnostic word. rx_enh_crc32_err (CRC error signal)
is sent to the FPGA fabric.
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English