Intel Cyclone 10 GX User Manual

Table 168. Supported PRBS Patterns
PRBS Pattern 10 bit PCS-PMA width 64 bit PCS-PMA width
PRBS7: x
7
+ x
6
+ 1 Yes
PRBS9: x
9
+ x
5
+ 1 Yes Yes
PRBS15: x
15
+ x
14
+ 1 Yes
PRBS23: x
23
+ x
18
+ 1 Yes
PRBS31: x
31
+ x
28
+ 1 Yes
Figure 189. PRBS9 Verify Serial Implementation
S0 S1 S4 S5 S8
PRBS Error
PRBS datain
The PRBS checker has the following control and status signals available to the FPGA
fabric:
•
rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It
stays high until you reset it with rx_prbs_err_clr.
•
rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to
allow you to capture it in the RX FPGA CLK domain.
•
rx_prbs_err_clr—Used to reset the rx_prbs_err signal.
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
5.2.2.7. Pseudo Random Pattern Verifier
The Pseudo Random Pattern (PRP) verifier is available for 10GBASE-R and 10GBASE-R
1588 protocol modes. The PRP verifier block operates in conjunction with the
descrambler. The PRP verifier monitors the output of the descrambler when block
synchronization is achieved.
The rx_prbs_err error signal is shared between the PRBS checker and the PRP
verifier.
The PRP verifier:
• Searches for a test pattern (two local faults, or all 0s) or its inverse
• Tracks the number of mismatches with a 16-bit error counter
5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English