• Set the Native PHY IP Core TX Channel bonding mode to Non Bonded .
4.
Connect the PLL IP core to the Native PHY IP core. Connect the tx_serial_clk
output port of the PLL to IP to the corresponding tx_serial_clk0 input port of
the Native PHY IP core. This port represents the input to the local CGB of the
channel. The tx_serial_clk for the PLL represents the high speed serial clock
generated by the PLL.
3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration
This configuration is an extension of the x1 non-bonded case. In the following
example, 10 channels are connected to two instances of the PLL IP core. Two PLL
instances are required because PLLs using the x1 clock network can only span the 6
channels within the same transceiver bank. A second PLL instance is required to
provide the clock to the remaining 4 channels.
Because 10 channels are not bonded and are unrelated, you can use a different PLL
type for the second PLL instance. It is also possible to use more than two PLL IP cores
and have different PLLs driving different channels. If some channels are running at
different data rates, then you need different PLLs driving different channels.
Figure 139. PHY IP Core and PLL IP Core Connection for Multi-Channel x1 Non-Bonded
Configuration
Transceiver PLL
Instance (5 GHz)
fPLL
Transceiver PLL
Instance (5 GHz)
fPLL
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the adjacent transceiver bank.
TX channels placed in the same transceiver bank.
3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
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