Intel Cyclone 10 GX User Manual

Figure 76. Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS)
Configuration
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
(10.3125 Gbps)
Serializer
Interlaken
Disparity Generator
Scrambler (3)
Descrambler (3)
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Interlaken
Disparity Checker
Block
Synchronizer (1)
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_clkout
Enhanced PCS
TX FIFO
Enhanced PCS
RX FIFO
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
FPGA
Fabric
tx_clkout
Parallel Clock (322.265625 MHz)
Parallel Clock (322.265625 MHz)
(5156.25 MHz) =
Data rate/2 (2)
Input Reference Clock
32-bit
data
32-bit
data
tx_coreclkin
322.265625 MHz
rx_coreclkin
322.265625 MHz
32
32
32
32
Notes:
1. Can be enabled or disabled based on the gearbox ratio selected
2. Depends on the value of the clock division factor chosen
3. To use the Scrambler and Descrambler, you must use a 66:32, 66:40, or 66:64 gear ratio and the Block Synchronizer must be enabled
2.9.1.1. How to Implement the Basic (Enhanced PCS) Transceiver Configuration
Rules in Cyclone 10 GX Transceivers
You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL
architecture, and the reset controller before implementing the Basic (Enhanced PCS)
Transceiver Configuration Rule.
1. Open the IP Catalog and select the Cyclone 10 GX Transceiver Native PHY IP.
Refer to Select and Instantiate the PHY IP Core on page 17 for more details.
2. Select Basic (Enhanced PCS) from the Transceiver Configuration Rules list
located under Datapath Options.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
Basic (Enhanced PCS) Transceiver Configuration Rules as a starting point. Or, you
can use the protocol presets described in Transceiver Native PHY Presets. You can
then modify the settings to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
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10 GX Transceiver PHY User Guide
159

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English