Intel Cyclone 10 GX User Manual

Figure 77. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) Configurations
Reconfiguration
Registers
NIOS
Hard Calibration IP
TX PMA
Serializer
tx_serial_data
tx_serial_clk0
(from TX PLL)
rx_cal_busy
tx_cal_busy
rx_serial_data
rx_control[19:0]
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
rx_parallel_data[127:0]
tx_control[17:0] tx_control[17:0]
tx_digital_resettx_digital_reset
tx_parallel_data[127:0]
reconfig_clk
reconfig_avmm
reconfig_reset
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
RX PMA
TX Enhanced PCS
RX Enhanced PCS
Deserializer
Clock
Generation
Block
rx_cdr_refclk0
CDR
rx_clkout
rx_coreclkin
rx_clkout
rx_coreclkin
rx_analog_reset
tx_analog_reset
rx_digital_resetrx_digital_reset
rx_parallel_data[127:0]
rx_control[19:0]
5. Configure and instantiate the PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP core to the PLL IP core and the reset controller.
Figure 78. Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design
Reset
Controller
Cyclone 10 Transceiver
Native PHY
Design
Testbench
32-bit data
(32:32
gearbox ratio)
PLL IP Core
8. Simulate your design to verify its functionality.
2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS)
This section contains the recommended parameter values for this protocol. Refer to
Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of
parameter values.
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Intel
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10 GX Transceiver PHY User Guide
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Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English