Intel Cyclone 10 GX User Manual

Table 141. General and Datapath Parameters
The first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and
datapath options to customize the transceiver.
Parameter Range
Message level for rule violations error, warning
Transceiver configuration rules Basic (Enhanced PCS)
PMA configuration rules Basic, GPON
Transceiver mode TX / RX Duplex, TX Simplex, RX Simplex
Number of data channels 1 to 12
Data rate GX transceiver channel: 1 Gbps to 12.5 Gbps
Enable datapath and interface reconfiguration On / Off
Enable simplified data interface On / Off
Table 142. TX PMA Parameters
Parameter Range
TX channel bonding mode Not bonded, PMA only bonding, PMA and PCS bonding
PCS TX channel bonding master Auto, 0 to n-1, n (where n = the number of data channels)
Actual PCS TX channel bonding master n-1 (where n = the number of data channels)
TX local clock division factor 1, 2, 4, 8
Number of TX PLL clock inputs per channel 1, 2, 3, 4
Initial TX PLL clock input selection 0
Enable tx_pma_clkout port On / Off
Enable tx_pma_div_clkout port On / Off
tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port On / Off
Enable rx_serialpbken port On / Off
Table 143. RX PMA Parameters
Parameter Range
Number of CDR reference clocks 1 to 5
Selected CDR reference clock 0 to 4
Selected CDR reference clock frequency For Basic (Enhanced PCS): Depends on the data rate
parameter
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual
Enable rx_pma_clkout port On / Off
Enable rx_pma_div_clkout port On / Off
rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable rx_pma_clkslip port On / Off
continued...
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Send Feedback
Intel
®
Cyclone
®
10 GX Transceiver PHY User Guide
161

Intel Cyclone 10 GX Specifications

General

Brand	Intel
Model	Cyclone 10 GX
Category	Transceiver
Language	English